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Showing posts with the label Computer Organization and Architecture

Flip-Flop

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SR FLIP-FLOP The SR Flip-Flop is bistable device having 2 inputs Set and Reset. The Set input (S) sets the device or produces the output 1, and the Reset input (R) resets the device or produces the output 0.  The Reset input is used to get back the flip flop to its original state from the current state with an output Q. This output depends on the set and reset conditions, which is either at the logic level 0 or 1.  The NAND Gate SR FLIP-FLOP We can implement the SR Flip-Flop by using two cross-coupled 2-input NAND gates together. In the SR Flip-Flop, from each output to one of the NAND gate inputs, feedback is connected. So, the device has two inputs, S and R and two outputs Q and Q'. The NAND Gate SR Flip-Flop is a basic Flip-Flop which provides feedback from both of its output back to its opposing inputs. This circuit is used to store single data bit in the memory circuit.So, the SR Flip-Flop. So, the SR Flip-Flop has three inputs, S , R and the output Q. The output Q is rel...

SR LATCH

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 SR Latch SR latch is also called as Set Reset Latch. This Latch effects the output as long as the Enable E is maintained at 1. The circuit has two inputs S and R. The circuit has two outputs Q(t) and Q'(t). The upper NOR Gate has two inputs R and the complement of the present state, Q(t)' and produces the next state Q(t+1) when Enable E is 1. Similarly the lower NOR Gate has two inputs S and present state Q(t) and produces the complement of the next state Q(t+1)' when Enable E is 1. We know that a two-input NOR Gate produces an output, which is the complement of the other output when one of the input is 0. Similarly produces 0 output, when one of the input is 1. When S is 1, the next state Q(t+1) has the value 1, irrespective of present state, Q(t) values. When R is 1, the next state Q(t+1) has the value 0, irrespective of present state, Q(t) values. At any time, both inputs cannot have the value 1, otherwise the value Q(t+1) is not defined. Table of SR-Latch: